1. Field of the Invention
The present invention relates to an LCD (Liquid Crystal Display) controller connected to a key matrix and to an LCD through terminals. This Patent Application is based on Japanese Patent Application No. JP 2007-129871. The disclosure thereof is incorporated herein by reference.
2. Description of Related Art
A general electronic apparatus to which an LCD controller is applied will be described. The electronic apparatus is provided with an LCD, a key matrix, and a microcomputer.
FIG. 1A shows an LCD panel 100 that is the above-mentioned LCD. The LCD panel 100 has LCD back electrodes and LCD front electrodes. In case of M time division, the LCD back electrodes are M division back electrodes (M is an integer of two or more). The LCD front electrodes are N division front electrodes (N is an integer of two or more).
The microcomputer is provided with M COM terminals as common (COM) outputs and N SEG terminals as segment (SEG) outputs. Below, the M COM terminals and the N SEG terminals are referred to as terminals COM0 to COM(M−1) and terminals SEG0 to SEG(N−1), respectively. The terminals COM0 to COM(M−1) are connected to the M back electrodes of the LCD panel 100, respectively. The terminals SEG0 to SEG(N−1) are connected to the N front electrodes of the LCD panel 100, respectively.
The microcomputer is provided with an LCD controller (not shown). The LCD controller executes an LCD display output process of periodically outputting a signal for one frame.
The LCD display output process will be described taking a case of generally used ⅓ bias and M time division as an example. As shown in FIG. 1B and FIG. 1C, supposing that a period of one frame is TF, a unit time of time division is TL, and M is four, TF is expressed by 4×TL.
As shown in FIG. 1B, the LCD controller outputs common signals to the terminals COM0 to COM(M−1). The common signal has a display drive voltage indicating a maximum value Vlcd, a minimum value Vgnd, and intermediate values between the maximum value Vlcd and the minimum value Vgnd, and the minimum value Vgnd of the display drive voltage shows a ground voltage. In case of ⅓ bias, the intermediate values are ⅓Vlcd and ⅔Vlcd. For example, the LCD controller outputs the maximum values Vlcd the terminals COM0 to COM(M−1) as the first to Mth values to in this order. Here, the LCD controller outputs the maximum value Vlcd of the display drive voltage to the terminals COM0 to COM(M−1) as a below-mentioned selection level, and immediately after, outputs the minimum value Vgnd to the terminals COM0 to COM(M−1). Moreover, the LCD controller outputs an intermediate value ⅓Vlcd to the terminals COM0 to COM(M−1) as a non-selection level, and immediately after, outputs an intermediate value ⅔Vlcd to the terminals COM0 to COM(M−1).
As shown in FIG. 1C, the LCD controller outputs segment signals to the terminals SEG0 to SEG(N−1). The segment signal has a display drive voltage indicating the maximum value Vlcd, the minimum value Vgnd, and the intermediate values ⅓Vlcd and ⅔Vlcd. The LCD controller outputs the minimum value Vgnd of the display drive voltage to the terminals SEG0 to SEG(N−1) as a below-mentioned selection level, and immediately after, outputs the maximum value Vlcd to the terminals SEG0 to SEG(N−1). Moreover, the LCD controller outputs the intermediate value ⅔Vlcd to the terminals SEG0 to SEG(N−1) as a non-selection level, and immediately after, outputs the intermediate value ⅓Vlcd to the terminals SEG0 to SEG(N−1).
Here, it is supposed that the common voltage indicating value (Vlcd, Vgnd) (⅓Vlcd, ⅔Vlcd) supplied to the terminals COM0 to COM(M−1) during a unit time TL is Vcom, and the segment voltage indicating value (Vlcd, Vgnd) (⅓Vlcd, ⅔Vlcd) supplied to the terminals SEG0 to SEG(N−1) during the unit time TL is Vseg. In this case, a relation shown in the following equation (1) is satisfied in the unit time TL. thus, charge remaining between the electrodes of the LCD panel 100 is negated.∫(Vcom−Vseg)dt=0  (1)
As shown in FIG. 1D, when the maximum value Vlcd of the display drive voltage is supplied to the terminal COM(I−1) (I is an integer satisfying 1≦I≦M) as a selection level, the back electrode corresponding to the terminal COM(I−1) is selected from among M back electrodes of the LCD panel 100. Moreover, when the minimum value Vgnd of the display drive voltage is supplied to the terminal SEG(J−1) (J is an integer satisfying 1≦J≦N) as the segment signal, the front electrode corresponding to the terminal SEG(J−1) is selected from among the N front electrodes of the LCD panel 100. Then, when the back electrode corresponding to the terminal COM(I−1) and the front electrode corresponding to the terminal SEG(J−1) are selected, display data corresponding to the common signal and the segment signal are displayed by using the back electrode and the front electrode. Otherwise, the display data is not displayed.
For example, as shown in FIG. 1E, when at the same time, the maximum value Vlcd of the display drive voltage is supplied to the terminal COM0 and the minimum value Vgnd of the display drive voltage is supplied to the terminals SEG0, SEG2, and SEG3, the display data is displayed by using the back electrodes and the front electrodes corresponding to the terminal COM0 and the terminals SEG0, SEG2, and SEG3. Similarly, when at the same time, the maximum value Vlcd is supplied to the terminal COM1 and the minimum value Vgnd is supplied to the terminals SEG1, SEG2, and SEG3, the display data is displayed by using the back electrodes and the front electrodes corresponding to the terminal COM1 and the terminals SEG1, SEG2, and SEG3. Moreover, when at the same time, the maximum value Vlcd is supplied to the terminal COM2 and the minimum value Vgnd is supplied to the terminals SEG0 and SEG1, the display data is displayed by using the back electrodes and the front electrodes corresponding to the terminal COM2 and the terminals SEG0 and SEG1. Furthermore, when at the same time, the maximum value Vlcd is supplied to the terminal COM3 and the minimum value Vgnd is supplied to the terminals SEG0, SEG1, and SEG3, the display data is displayed by using the back electrodes and the front electrodes corresponding to the terminal COM3 and the terminals SEG0, SEG1, and SEG3, respectively.
FIG. 2A shows a key matrix 200 that is the above-mentioned key matrix. The key matrix 200 has keys in a matrix of m rows and n columns (m and n are integers of one or more).
The microcomputer is further provided with a key sense circuit (not shown), n key source (KS) terminals, and m key return (KR) terminals. Below, n KS terminals and m KR terminals are referred to as terminals KS0 to KS(n−1) and terminals KR0 to KR(m−1), respectively. The terminals KS0 to KS(n−1) are connected to the column of the key matrix 200, respectively. The terminals KR0 to KR(m−1) are connected to the row of the key matrix 200, respectively.
A power supply is connected between the terminals KR0 to KR(m−1) and the row of the key matrix 200 through m resistance elements, respectively. In this case, the terminals KR0 to KR(m−1) are supplied with the maximum value Vlcd of the display drive voltage by the power supply.
The key matrix 200 further has an N-channel MOSFET and is turned on when the key at the ith row and the jth column (i is an integer satisfying 1≦i≦m, and j is an integer satisfying 1≦j≦n) is operated and connects the terminal KR(i−1) and the terminal KS(j−1). The terminal KS(j−1) is used as an N-channel open drain so that even if the keys are operated simultaneously, it may not cause a problem. When the key of the ith row and the jth column is operated, if the minimum value Vgnd of the display drive voltage is supplied to the terminal KS(j−1); the minimum value Vgnd is supplied to the terminal KR(i−1).
The key sense circuit executes a key source (KS) output process. Below, the KS output process will be described.
Now, it is supposed that none of the keys of the key matrix 200 of m rows and n columns is operated. This state is referred to as a key-in wait state.
In the key-in wait state, as shown in FIG. 2A, the key sense circuit continues to output the minimum value Vgnd of the display drive voltage to the terminals KS0 to KS (N−1). Here, it is supposed that a signal level of a signal indicating the maximum value Vlcd of the display drive voltage is a high level (High) “1,” and a signal level of a signal indicating the minimum value Vgnd of the display drive voltage is a low level (Low) “0.” As described above, the maximum value Vlcd is supplied to the terminals KR0 to KR(m−1). When all the signal levels of the signals supplied to the terminals KR0 to KR(M−1) are “1,” the key sense circuit recognizes that none of the keys in the matrix of m rows and n columns is operated.
When the user operates one key at the ith row and the jth column, the minimum value Vgnd is supplied to the terminal KR(i−1) if the minimum value Vgnd is supplied to the terminal KS(j−1) during a KS output period. Since the signal level of the signal supplied to the terminal KR(i−1) is Low “0,” the key sense circuit discriminates the key in the ith row and the jth column as the key operated by the user among the keys in the matrix of m rows and n columns. In this case, the interrupt is generated.
When the interrupt is caused, a key scan process is executed (this is called a key scan state).
In the key scan state, as shown in FIG. 2B, the key sense circuits output the pulse signals pls which vary between the maximum value Vlcd “1” and the minimum value Vgnd “0” of the display drive voltage to the terminals KS0 to KS(n−1) at respective different timings. For example, the pulse signal pls shows the minimum value Vgnd “0,” and the key sense circuit outputs the first to nth pulse signals pls to the terminals KS0 to KS(n−1) in this order.
Now, it is supposed that the matrix is composed of three rows and three columns, the first, the second, and the third rows of the first, the second, and the third columns are buttons A to C, buttons D to F, and buttons G to I, respectively. In this case, as shown in FIG. 2C, in the key scan state, a first determination is done as follows. That is, when the minimum value Vgnd “0,” the maximum value Vlcd “1” and the maximum value Vlcd “1” of the display drive voltage are outputted to the respective. terminals SEG/KS0 to SEG/KS2 (Step S101), the microcomputer determines that the user operated a button A (Step S103) if the minimum value Vgnd “0” is supplied to the terminal KR0 (Step S102—YES). A second determination is done as follows. that is, when the maximum value Vlcd “1” the minimum value Vgnd “0” and the maximum value Vlcd “1” are outputted to the respective terminals KS0 to KS2 (Steps S101, S102—NO, and S104), the microcomputer determines that the user operates a button B (Step S106), if the minimum value Vgnd “0” is supplied to the terminal KR0 (Step S105—YES). A third determination is done as follows. That is, when the maximum value Vlcd “1” the maximum value Vlcd “1,” and the minimum value Vgnd “0” are outputted to the respective terminals KS0 to KS2 (Steps S101, S102—NO, S104, S105—NO, and S107), the microcomputer determines that the user operated a button C (Step S109), if the minimum value Vgnd “0” is supplied to the terminal KR0 (Step S108—YES) As the fourth determination, when the microcomputer determines that the buttons A to C were not operated (Step S110), the Steps S101 to S110 will be executed for the buttons D to F and the buttons G to I.
From the above, subjects that need to be done for the above-mentioned electronic apparatus are summarized below. First, as subjects needed for the KS output process, followings are desired.
[I] In the key-in wait state, the LCD controller must continue to output the minimum value Vgnd “0” of the display drive voltage to the terminals KS0 to KS(N−1) and to wait generation of interrupt (a state in which the CPU is performing no key scan).
[II] In the key scan state, the minimum value Vgnd “0” of the display drive voltage must be outputted to the terminals KS0 to KS(N−1) at respective different timings as pulse signals pls.
[III] Even if the keys in the key matrix 200 are operated simultaneously, no problem is caused (the terminals KS0 to KS(n−1) must be N-channel open drains).
Moreover, in case of ⅓ bias, as subjects that are needed for a common output and a segment output, the followings are desired.
[IV] When displaying the display data by using the electrodes of the LCD panel 100, the maximum value Vlcd of the display drive voltage must be outputted to the terminal COM(I−1) (I is an integer satisfying 1≦I≦M), and the minimum value Vgnd of the display drive voltage is outputted to the terminal SEG(J−1) (J is an integer satisfying 1≦J≦N).[V] When not displaying the display data by using the electrodes of the LCD panel 100, an intermediate value ⅓Vlcd of the display drive voltage must be outputted to the terminal COM(I−1) (a ⅓ bias mode).[VI] In order to negate a residual charge between the electrodes of the LCD panel 100, the above-mentioned equation (1) must be satisfied in one frame.
In recent years, miniaturization of chips and packages that are used for the microcomputer is required. For example, as shown in FIG. 3, Japanese Patent Application Publication (JP-A-Heisei 3-233623) describes a microcomputer 300 in which the number of terminals is reduced.
The microcomputer 300 is provided with the terminals COM0 to COM(M−1) and the terminals KR0 to KR(m−1). Moreover, the microcomputer 300 is provided with N segments (SEG)/key source (KS) terminals instead of the terminals SEG0 to SEG(N−1) and the terminals KS0 to KS(N−1). Below, the N SEG/KS terminals are referred to as terminals SEG/KS0 to SEG/KS(N−1). Here, among the terminals SEG/KS0 to SEG/KS(N−1), the terminals SEG/KS0 to SEG/KS(n−1) are connected to columns of the key matrix 200. Thus, the terminals SEG/KS0 to SEG/KS(N−1) are shared as the terminals SEG0 to SEG(N−1) and the terminals KS0 to KS(n−1).
The microcomputer 300 is provided with m voltage comparator circuits 301 that are connected between the terminals KR0 to KR(m−1) and the rows of the key matrix 200, respectively, and m flip-flop circuits 302 that are connected between the terminals KR0 to KR(m−1) and the m voltage comparator circuits 301, respectively. The m flip-flop circuits 302 are used as a memory section.
The microcomputer 300 periodically outputs common signals and the segment signals for one frame. In this case, the one frame includes an LCD display output period when the above-mentioned LCD display output process is executed and the KS output period when a below-mentioned key source (KS) output process is executed.
First, the LCD display output process is executed. During the LCD display output period, the microcomputer 300 outputs the common signals to the terminals COM0 to COM(M−1), and outputs the segment signals to the terminals SEG/KS0 to SEG/KS(N−1).
Next, the KS output process is executed.
The microcomputer 300 outputs the intermediate value ⅓Vlcd to the terminals COM0 to COM(M−1) as a non-selection level, for example, during the KS output period of an odd-number frame, and outputs the intermediate value ⅔Vlcd to the terminals COM0 to COM(M−1) during the KS output period of an even-number frame.
During the KS output period in a first frame, the microcomputer 300 outputs the intermediate value ⅓Vlcd of the display drive voltage to the terminal SEG/KS0, and outputs the intermediate value ⅔Vlcd to the terminals SEG/KS other than it. Next, during the KS output period in a second frame, the microcomputer 300 outputs the intermediate value ⅔Vlcd of the display drive voltage to the terminal SEG/KS0, and outputs the intermediate value ⅓Vlcd to the terminals SEG/KS other than it. Similarly, during the KS output period in the (2N−1)th frame, the microcomputer 300 outputs the intermediate value ⅓Vlcd to the terminal SEG/KS(N−1), and outputs the intermediate value ⅔Vlcd to the terminals SEG/KS other than it. Next, during the KS output period in the 2Nth frame, the microcomputer 300 outputs the intermediate value ⅔Vlcd to the terminal SEG/KS(N−1), and outputs the intermediate value ⅓Vlcd to the terminals SEG/KS other than it.
When the user operates the key in the ith row and the jth column (i is an integer satisfying 1≦i≦m, and j is an integer satisfying 1≦j≦n), an ith voltage comparator circuit 301 is supplied with the intermediate value ⅓Vlcd if the intermediate value ⅓Vlcd of the display drive voltage is supplied to the terminal KS(j−1) during the KS output period. The ith voltage comparator circuit 301 outputs the intermediate value ⅓Vlcd to the terminal KS(j−1) as the minimum value Vgnd “0” through the ith flip-flop 302, while the voltage comparator circuits 301 other than the above-mentioned ith voltage comparator circuit 301 output the intermediate value ⅔Vlcd to the terminals KS other than the terminal KS(j−1) as the maximum value Vlcd “1” through the flip-flops 302 other than the above-mentioned ith flip-flop 302. Thus, the microcomputer 300 discriminates the key operated by the user.
However, there are the following problems in the microcomputer 300.
First, in the microcomputer 300, when the key operated by the user is discriminated in the key scan state, as described above, a constant value of the display drive voltage (the intermediate value ⅓Vlcd or the intermediate value ⅔Vlcd) is supplied to the key matrix 200 through the terminals SEG/KS0 to SEG/KS(N−1) during the KS output period. In this case, the constant value is also supplied to the LCD panel 100 from the terminals SEG/KS0 to SEG/KS (N−1). For this reason, charge will remain in the front electrodes of the LCD panel 100. Thus, it is desired to reduce the charge remaining in the LCD panel 100 as well as reduction of the number of the terminals.
Second, in the microcomputer 300, 2N frames are regarded as one period, and the intermediate value ⅓Vlcd is outputted to the respective terminals SEG/KS0, SEG/KS1, . . . , SEG/KS(N−1) during the KS output period of the first, third, . . . , (2N−1)th frames. As a result, when the above-mentioned N is enlarged (when the number of the terminals SEG/KS is increased), a very large time is required to perform the key scan. For this reason, it requires a very large time to discriminate the key operated by the user from among the keys of the key matrix 200. Therefore, there is a possibility that the key scan may not be executed well.
Third, the microcomputer 300 needs the m voltage comparator circuits 301 for converting the intermediate value ⅓Vlcd and the intermediate value ⅔Vlcd into the minimum value Vgnd “0” and the maximum value Vlcd “1,” respectively, and outputting them to the terminals KR0 to KR(m−1).